1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having charge storage means which is two-dimensionally discrete, for example, a charge trap in the nitride film in a metal oxide nitride oxide semiconductor (MONOS) type device or metal nitride oxide semiconductor (MNOS) type device, wherein the device records or erases data by injecting charges into or taking out charges from the charge storage means, and a process for fabricating the non-volatile semiconductor memory device.
2. Description of the Related Art
As non-volatile semiconductor memory devices, there are known floating gate (FG)-type memory devices in which a charge storage means (floating gate) for storing charges is two-dimensionally continued, and MONOS-type memory devices and MNOS-type memory devices in which a charge storage means (e.g., carrier trap) is two-dimensionally discrete.
In the MONOS-type memory devices, on a semiconductor substrate where a channel is formed, an oxide nitride oxide (ONO) film and a gate electrode are stacked on one another, and, in the substrate surface regions on both sides of the resultant stacked layer pattern, source-drain regions each having the opposite conductivity to the channel are formed.
Writing is conducted by injecting charges from the substrate into an insulating film having charge storage ability. On the other hand, erasing is conducted by taking out the stored charges to the substrate or injecting into the insulating film charges having the opposite polarity to the stored charges.
In the above-mentioned conventional MONOS-type memory devices, a channel is formed on the surface of a flat single crystal silicon substrate.
Further, in recent years, with respect to the MONOS-type memory device having a channel in the semiconductor substrate and having silicon nitride (SiNx) as a charge storage layer, a semiconductor memory device has been reported in which electrons are locally written in a source end or a drain end using hot electron injection to make it possible to store charges independently, enabling recording of 2 bits per memory device (see Boaz Eitan, et al., Extended Abstracts of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 522).
However, when a channel is formed on the surface of a flat single crystal silicon substrate, for improving the degree of integration of the data recording density, the size per unit memory device in the substrate must be scaled down.
Therefore, for achieving the scaled-down semiconductor memory device, the length of the channel (channel length) between the source region and the drain region in the semiconductor memory device must be shortened. However, the shortening of the gate length causes a so-called short channel effect, and typically, when the gate length is 0.1 μm or shorter, the transistor properties of the semiconductor memory device disadvantageously become poor.
In addition, in the above-mentioned semiconductor memory device in which a channel is formed in the semiconductor substrate and electrons are locally written in the source end or the drain end in the discrete charge storage layer using hot electron injection to enable recording of 2 bits per unit memory device, when the channel length is shortened, the charge storage regions of the source end and the drain end in which electrons are locally written overlap, so that the two different regions that electrons are separately written cannot be distinguished from each other, making it impossible to perform the operation of recording of 2 bits per unit memory device.